1) Field of the Invention
The present invention relates to memory in general and in particular to memories suitable for use with computers and computer based devices such as Network Processors (NP).
2) Prior Art
The use of memories to provide storage for network devices such as switches, Network Processors, etc., are well known in the prior art. One of the requirements of such a memory is that it provides sufficient bandwidth to meet the bandwidth requirements of the device to which it provides storage. For relatively low bandwidth devices a single memory unit may be sufficient. The design of a controller to allow access to the single memory unit is usually straight forward and presents few, if any, challenges.
For relatively high bandwidth devices, such as devices used in communications networks including the worldwide web better known as the internet, multiple memory units are often required. Arguably, multiple memories should provide higher bandwidth. But experience has shown that unless the device and method used to access the memory units are properly designed the increased throughput is often not realized.
As a consequence one of the problems that designers encounter with multiple memory units is to find a way to control them so that the full bandwidth capabilities are realized. Failure to design an appropriate controller could lead to reduction in the available bandwidth.
In addition, a well designed access mechanism allows one to use relatively slow memory units, such as DDR DRAMs, for high speed applications. Without the use of an appropriate access mechanism to augment performance of the DDR DRAM one may have to use a higher performance memory such as SRAMs or the like. The price of SRAM is usually higher than that of DDR DRAMs. This price differential could be a negative; since the overall cost of a machine is based, in part, on unit cost used in the machine.
In view of the above there is a need to provide memory subsystems in which the available bandwidth is at its maximum.